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HT46R73D-1
Dual Slope A/D Type MCU with LCD
Technical Document
* Tools Information * FAQs * Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series - HA0007E Using the MCU Look Up Table Instructions - HA0049E Read and Write Control of the HT1380
Features
* Operating voltage: * On-chip RC or crystal oscillator * HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 12 bidirectional I/O lines and two ADC input * One external interrupt input shard with an I/O lines * One 8-bit and one 16-bit programmable timer/event
consumption
* Voltage regulator (3.3V) and charge pump * Embeded voltage reference generator (1.5V) * 4-level subroutine nesting * Bit manipulation instruction * 14-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock
counter with overflow interrupt a 7-stage pre-scalar
* LCD driver with 164, 173 or 172 segments * 4K15 program memory with partial lock function * 968 data memory RAM * Single differential input channel dual slope Analog to
at VDD=5V
* 63 powerful instructions * All instructions in 1 or 2 machine cycles * Low voltage reset/detector function * 52-pin QFP package
Digital Converter with Operational Amplifier.
* Watchdog Timer with regulator power * Buzzer output * Internal 12kHz RC oscillator
General Description
The HT46R73D-1 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for A/D with LCD applications that interface directly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Dual slope A/D converter, LCD display, HALT and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of these devices to suit for a wide range of AD with LCD application possibilities such as sensor signal processing, scales, consumer products, subsystem controllers, etc.
Rev. 1.10
1
July 4, 2007
HT46R73D-1
Block Diagram
In te rru p t C ir c u it P ro g ra m ROM P ro g ra m C o u n te r STACK IN T C TM R 0C TM R0 M U X M U X fS
YS
P r e s c a le r P A 4 /T M R 0
In t. R C
OSC
In s tr u c tio n R e g is te r
TM R 1C TM R1 MP M U X D a ta M e m o ry W DT P r e s c a le r
M U
P A 5 /T M R 1 X P r e s c a le r M U X fS
YS
/4
In t. R C O S C
fS W DT M U X
YS
/4 In t. R C O S C
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
PBC PB STATUS PAC BP PA
P o rt B
PB0~PB3 PA PA PA PA PA PA PA PA 0 /B Z 1 /B Z 2
S h ifte r P o rt A
OSC2
OS RE VD VS S
D
S
C1
ACC
HALT
LCD M e m o ry
E N /D IS
3 4 /T M R 0 5 /T M R 1 6 /IN T 7
L V D /L V R DO DO DO DC DS DS DS PA PA PA HO RR RC CC O P N P
VDD VOCHP VOREG
C h a rg e Pum p
L C D D r iv e r
R e g u la to r
C O M 0~C O M 2 C O M 3 /S E G 1 6
SEG 0~SEG 15
1 -C h a n n e l D u a l- S lo p e C o n v e rte r w ith O P
Pin Assignment
P A 4 /T P A 5 /T PA6 D
52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10
PA PA O O
SC SC RE 0 /B 1 /B PA PA MR MR /IN PA VS VD S S T Z Z 7 1 0 3 2 1 2
A VO CH CH VO VO A DO DO DO DC D D
VD BG PC PC CH RE VS PA PA PA HO SR SR O
D P P G N R C P P S
39 38 37 36 35
1
2
H T 4 6 R 7 3 D -1 5 2 Q F P -A
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
34 33 32 31 30 29 28 27
SE SE SE SE SE SE SE SE SE SE SE SE SE
G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G 10 G 11 G 12
SE SE SE CO CO CO CO VL PB PB PB PB DS G1 G1 G1 M3 M2 M1 M0 CD 3 0 1 CC 2 5 /S E G 1 6 4 3
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HT46R73D-1
Pin Description
Pin Name PA0/BZ PA1/BZ PA2 PA3 PA4/TMR0 PA5/TMR1 PA6/INT PA7 PB0~PB3 VLCD COM0~COM2 COM3/SEG16 SEG0~SEG15 VOBGP VOREG VOCHP CHPC1 CHPC2 DOPAN, DOPAP, DOPAO, DCHOP DSRR, DSRC, DSCC OSC1 OSC2 RES VDD VSS AVDD AVSS I/O Options Description Bidirectional 8-bit input/output port. Each individual bit on this port can be configured to have a wake-up function using a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. The BZ, BZ, TMR0, TMR1 and INT are pin-shared with PA0, PA1, PA4, PA5 and PA6 respectively. Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. LCD power supply COM0~COM3 are the LCD common outputs. An LCD duty-cycle configuration option determines. When 1/3, 1/2 duty is selected, the COM3/SEG16 is configured as SEG16. LCD driver outputs for the LCD panel segments. Band gap voltage output pin. (for internal use) Regulator output 3.3V Charge pump output (a capacitor is required to be connected) Charge pump capacitor, positive Charge pump capacitor, negative Dual Slope converter pre-stage OPA related pins. DOPAN is the OPA Negative input pin, DOPAP is the OPA Positive input pin, DOPAO is the OPA output pin and DCHOP is the OPA Chopper pins. Dual slope AD converter main function RC circuit. DSRR is the input or reference signal, DSRC is the Integrator negative input, and DSCC is the comparator negative input. OSC1, OSC2 are connected to an external RC network or crystal for the internal system clock. The OSC2 pin can be used to monitor the system clock at 1/4 frequency. Schmitt trigger reset input, active low Positive power supply Negative power supply, ground Analog positive power supply Analog negative power supply, ground
I/O
Wake-up Pull-high Buzzer
I/O I O
Pull-high 3/4 1/2, 1/3 or 1/4 Duty Segment Output 3/4 3/4 3/4 3/4 3/4 3/4
O AO O O 3/4 3/4
AI/AO
AI/AO
3/4
I O I 3/4 3/4 3/4 3/4
Crystal or RC 3/4 3/4 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT46R73D-1
D.C. Characteristics
Test Conditions Symbol Parameter VDD VDD Operating Voltage 3/4 3/4 5V 3V 5V 3V 5V Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=8MHz, analog block off No load, fSYS=4MHz, ADC block off No load, fSYS=2MHz, ADC block off VREGO=3.3V, fSYS=4MHz, ADC on, ADCCCLK= 125kHz (all other analog devices off) No load, system HALT, LCD off at HALT No load, system HALT, LCD off at HALT, ADC off No load, system HALT, LCD off at HALT, ADC off No load, system HALT, LCD on at HALT, 1/2 bias, VLCD=VDD No load, system HALT LCD on at HALT, 1/3 bias, VLCD=VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 4 0.8 2.5 0.5 1.5 5.5 5.5 8 1.5 4 1 3 V V mA mA mA mA mA Min. Typ. Max. Unit Ta=25C
IDD1
Operating Current (Crystal) Operating Current (Crystal OSC or RC OSC) Operating Current (Crystal OSC or RC OSC)
IDD2
IDD3
IDD4
Operating Current (Crystal OSC or RC OSC)
5V
3/4
3
5
mA
ISTB1
Standby Current (WDT Disable) Standby Current (WDT Enable)
3V 5V 3V 5V
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 0 2 2.2 4 10
3/4 3/4 2.5 8 2 6 17 34 13 28 3/4 3/4 3/4 3/4 3/4 2.1 2.3 8 20 -4 -10 420 700
1 2 5 15 5 10 30 60 25 50 0.3VDD VDD 0.4VDD VDD VDD 2.2 2.4 3/4 3/4 3/4 3/4 3/4 3/4
mA mA mA mA mA mA mA mA mA mA V V V V V V V mA mA mA mA mA mA
ISTB2
ISTB3
Standby Current (WDT Disable In- 3V ternal RC 12kHz OSC ON) 5V Standby Current (WDT Disable In- 3V ternal RC 12kHz OSC ON) 5V Standby Current (WDT Disable In- 3V ternal RC 12kHz OSC ON) 5V Input Low Voltage for I/O Ports, TMR0, TMR1 and INT Input High Voltage for I/O Ports, TMR0, TMR1 and INT Input Low Voltage (RES) Input High Voltage (RES) LCD Highest Voltage Low Voltage Reset Low Voltage Detector I/O Port Segment Logic Output Sink Current I/O Port Segment Logic Output Source Current LCD Common and Segment Current 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V 5V
ISTB4
ISTB5
VIL1 VIH1 VIL2 VIH2 VLCD VLVR VLVD IOL1
IOH1
VOH=0.9VDD
-2 -5 210 350
IOL2
VOL=0.1VDD
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HT46R73D-1
Test Conditions Symbol Parameter VDD IOH2 LCD Common and Segment Current Pull-high Resistance of I/O Ports 5V Charge Pump and Regulator VCHPI VREGO VREGDP1 Regulator Output Voltage Drop (Compare with No Load) VREGDP2 Dual Slope AD, Amplifier and Band Gap VRFGO VRFGTC VADOFF VICMR Reference Generator Output Reference Generator Temperature Coefficient Input Offset Range Common Mode Input Range 3/4 3/4 3/4 3/4 3/4 @3.3V @3.3V 3/4 Amplifier, no load Integrator, no load 1.45 3/4 3/4 0.2 1 1.5 50 500 3/4 3/4 1.55 3/4 800 VREGO-1 VREGO-0.2 V Ppm/C mV V V 3/4 Input Voltage Output Voltage 3/4 3/4 3/4 Charge pump on Charge pump off No load VDD=3.7V~5.5V Charge pump off Current10mA VDD=2.4V~3.6V Charge pump on Current6mA 2.2 3.7 3 3/4 3/4 3/4 3.3 100 3.6 5.5 3.6 3/4 V V V mV 3V 5V 3V 3/4 3/4 Conditions VOH=0.9VDD -80 -180 20 10 -160 -360 60 30 3/4 3/4 100 50 mA mA kW kW Min. Typ. Max. Unit
RPH
3/4
100
3/4
mV
A.C. Characteristics
Test Conditions Symbol Parameter VDD System Clock (RC OSC) fSYS System Clock (Crystal OSC) 3/4 3/4 3/4 3V Internal RC OSC 5V fTIMER Timer I/P Frequency (TMR0/TMR1) 3/4 3V 5V tRES tSST tLVR tINT External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width 3/4 3/4 3/4 3/4 2.2V~5.5V 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 3/4 Conditions 2.2V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 400 400 400 3/4 3/4 0 45 32 1 3/4 0.25 1 3/4 3/4 3/4 12 15 3/4 90 65 3/4 1024 1 3/4 4000 4000 8000 3/4 3/4 4000 180 130 3/4 3/4 2 3/4 Min. Typ. Max.
Ta=25C Unit kHz kHz kHz kHz kHz kHz ms ms ms tSYS ms ms
fINRC
tWDTOSC Watchdog Oscillator Period
Note: tSYS= 1/fSYS
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HT46R73D-1
Functional Description
Execution Flow The system clock is derived from either a crystal or an external RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 12 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
T1 T2 T3 T4 T1 T2
The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
T3
T4
T1
T2
T3
T4
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter Mode *11 Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow ADC Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine *11 #11 S11 0 0 0 *9 #9 S9 *8 #8 S8 0 0 0 0 0 *10 0 0 0 0 0 *9 0 0 0 0 0 *8 0 0 0 0 0 *7 0 0 0 0 0 *6 0 0 0 0 0 *5 0 0 0 0 0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 0 *1 0 0 0 0 0 *0 0 0 0 0 0
Program Counter+2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
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July 4, 2007
HT46R73D-1
Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits which are addressed by the program counter and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H * Location 010H
Location 010H is reserved for the ADC interrupt service program. If an ADC interrupt occurs, and if the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Table location
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
Location 004H is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 4 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the program counter is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 4 return addresses are stored).
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
000H 004H 008H 00C H 010H 100H 1FFH nFFH FFFH L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 5 b its N o te : n ra n g e s fro m 1 to E D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e A D C In te r r u p t S u b r o u tin e L o o k - u p T a b le ( 2 5 6 W o r d s ) P ro g ra m M e m o ry
Program Memory
Instruction(s) TABRDC [m] TABRDL [m]
Table Location *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits 7 P11~P8: Current program counter bits
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HT46R73D-1
Data Memory - RAM Bank 0 of the data memory has a capacity of 1238 bits, and is divided into two functional groups, namely the special function registers of 278 bit capacity and the general purpose data memory of 968 bit capacity. Most locations are readable/writable, although some are read only. The special function register are overlapped in all banks. Any unused space before 20H is reserved for future expanded usage, reading these locations will get 00H. The general purpose data memory, addressed from 20H to 7FH , is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions. They are also indirectly accessible through the memory pointer registers, MP0 and MP1.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H W DTC W DTD IN T C 1 CHPRC G e n e ra l P u rp o s e D a ta M e m o ry (9 6 B y te s ) :U nused R e a d a s "0 0 " ADCR R e s e rv e d ADCD TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH MODE STATUS IN T C 0
Bank 1 contains the LCD Data Memory locations. After first setting up BP to the value of 01H to access Bank 1 this bank must then be accessed indirectly using the Memory Pointer MP1. With BP set to a value of 01H, using MP1 to indirectly read or write to the data memory areas with addresses from 40H~50H will result in operations to Bank 1. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of BP. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The memory pointer register (MP0, MP1) are 7-bit registers. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status
7FH
RAM Mapping
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HT46R73D-1
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4 Interrupts The device provides one external interrupts, two internal timer/event counter interrupts and the ADC interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/ disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked, by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC 0 (0BH) Register Bit No. 0 1~3, 5~7 4 Label EADI 3/4 ADF Function Controls the ADC interrupt (1=enabled; 0:disabled) Unused bit, read as 0 ADC request flag (1=active; 0=inactive) INTC 1 (1EH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
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HT46R73D-1
certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All interrupts will provide a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the Program Memory. Only the contents of the program counter is pushed onto the stack. If the contents of the register or of the status register is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. An external interrupt is triggered by an edge transition on INT (A configuration option selects: high to low, low to high, both low to high and high to low), and the related interrupt request flag (EIF; bit 4 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H occurs. The interrupt request flag (EIF) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 08H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 6 of INTC0) and its subroutine call location is 0CH. The A/D Converter interrupt is initialized by setting the A/D Converter clock interrupt request flag (ADF; bit 4 of INTC1), that is caused by an A/D conversion done signal. After the interrupt is enabled, and the stack is not full, and the ADF bit is set, a subroutine call to location 10H occurs. The related interrupt request flag (ADF) is reset and the EMI bit is cleared to disable further maskable interrupts. During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the Rev. 1.10 10 latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source External interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow ADC interrupt Priority 1 2 3 4 Vector 04H 08H 0CH 10H
Once the interrupt request flags (ADF, T0F, T1F, EIF) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Oscillator Configuration The device provides three oscillator circuits, an external RC oscillator, a crystal oscillator and an internal RC 12kHz oscillator (Int. RCOSC). The external RC oscillator and a crystal oscillator signal are used for the system clock and the internal 12kHz RC oscillator is designed for timing purposes. In the IDLE mode, the IRC clock source is enabled (IRCC=0), the system oscillator stop running, but the internal RC oscillator (Int.RCOSC) still continuously keep free running. In HALT mode, if the WDT is disabled, the IRC clock source is disabled (IRCC=1), both the system oscillator and internal RC oscillator stop running, but if the WDT is enabled, the internal RC oscillator will always keep free running. In the HALT mode, if the IRC clock source is disabled, with bit IRCC=0, both the system oscillator and the internal RC oscillator will stop running. However, if the WDT is enabled, the internal RC oscillator will continuously free run. The system can be woken-up from either the IDLE or HALT mode by the occurrence of an interrupt, a high to low transition on any of the Port A pins, a WDT overflow or a timer overflow and request flag is set (0(R)1).
V C1 470pF OSC1 R C2 R1 OSC2 C r y s ta l O s c illa to r fS Y S /4 N M O S o p e n d r a in OSC2 RC O s c illa to r
OSC DD
OSC1
System Oscillator July 4, 2007
HT46R73D-1
If the crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (if the oscillator can be disabled by options to conserve power). If an external RC oscillator is used, an external resistor between OSC1 and VSS is required to achieve oscillation, the value of which must be between 100kW to 2.4MW. The system clock divided by 4, which can be monitored on pin OSC2, can be used for external logic synchronization purposes. The Internal RC oscillator (Int.RCOSC) is a free running on-chip RC oscillator, requiring no external components. Even if the system enters the Power Down Mode, and the system clock is stopped, the internal RC oscillator continues to run with a period of approximately 65ms at 5V if either the WDT or IRC clock is enabled. The internal RC oscillator can be disabled by a configuration option and by clearing the IRCC bit to 0 to conserve power. Watchdog Timer - WDT The WDT is implemented using a dedicated internal RC oscillator (Int. RCOSC, note: the WDTOSC described in this document represents the same oscillator as the Int.RCOSC) or the instruction clock which is the system Bit No. Label clock/4. The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by a configuration option. If the watchdog timer is disabled, the WDT timer will have the same manner as in the enable-mode except that the timeout signal will not generate a chip reset. So in the watchdog timer disable mode, the WDT timer counter can be read out and can be cleared. This function is used for the application program to access the WDT frequency to get the temperature coefficient for analog component adjustment. The WDT oscillator needs to be disabled/enabled by the special function registers(WDTC :WDTOSC), for power saving reasons. There are 2 registers related to the WDT function, WDTC and WDTD. The WDTC register can control the WDT oscillator enable/disable and the WDT power source. WDTD is the WDT counter readout register. WDTPWR can be used to choose the WDT power source, the default source is VOCHP. The main purpose of the regulator is to be used for the WDT Temperature-coefficient adjustment. In this case, the application program should enable the regulator before switching to the Regulator source. The WDTOSC can be used to enable or disable the WDT OSC (12kHz). If the application does not use the WDT OSC, then it needs to disable it in order to save power. When WDTOSC is disabled, then it is actually turned off, regardless of the IRCC setting. When the WDTOSC is enabled, the Power Down mode situation will be defined by the IRCC registers. Function
0~1
The WDT Power source selection. (WDTPWR1:0)= 01: WDT power comes from VOCHP WDTPWR0~ 10: WDT power comes from regulator WDTPWR1 00/11: WDT power comes from VOCHP strongly recommend use to use 01 for VOCHP prevent the noise to let the WDT lose the power WDTOSC0~ WDTOSC1 3/4 The WDT oscillator enable/disable (WDTOSC1:0)= 01: WDT OSC disable10: WDT OSC enable 00/11: WDT OSC enable strongly recommend use to use 10 for WDT OSC enable Reserved WDTC (1CH) Register
2~3 4~7
Note: WDTOSC registers initial value will be set to enable (1,0), if both WDT option enable and WDT clock option set to WDT, otherwise, it will be set to disable (0,1)
Bit No. 0~7
Label
Function
WDTPWR0~ The WDT counter data value. WDTPWR7 This register is read only. Its used for temperature adjusting. WDTD (1DH) Register
The WDT clock (fS1) is further divided by an internal counter to give longer watchdog time-outs., In this device, the division ratio can be varied by selecting different configuration options to give 213 to 216 division ration range.
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VOCHP VOREG W DT PW R W DT OSC C L R W D T 1 F la g C L R W D T 2 F la g 1 /2 In s tr u c tio n s W DT OSC fS
YS
C o n tro l L o g ic W D T S o u rc e C o n fig u r a tio n O p tio n fS
1
W DTOSC E n a b le
/4
CLR 1 6 - B it C o u n te r b15 b4~b11 D a ta B u s W D T D iv is io n C o n fig u r a tio n O p tio n fS 1 /2
13
b0
W DT E N /D IS
W D T T im e - o u t
~ fS 1 /2
16
Watchdog Timer Once the internal RC oscillator, which has a nominal period of 65ms, is selected, it is then divided by a value which ranges from 212~215 the exact value of which is determined by a configuration option, to obtain the actual WDT time-out period. The minimum period of the WDT time-out period is about 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By using the related WDT configuration option, longer time-out periods can be realized. If the WDT time-out is selected to be 215, the maximum time-out period is divided by 215~216which will give a time-out period of about 2.3s~4.7s. The WDT clock source may also come from the instruction clock, in which case the WDT will operate in the same manner except that in the Power Down mode the WDT may stop counting and lose its protecting purpose. In this situation the device can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (Int.RC OSC) is strongly recommended, since the HALT instruction will stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT or IDLE mode, the overflow initializes a warm reset, and only the PC and SP are reset to zero. There are three methods to clear the contents of the WDT, an external reset (a low level on RES), a software instruction or a HALT instruction. There are two types of software instructions; the single CLR WDT instruction, or the pair of instructions 3/4 CLR WDT1 and CLR WDT2. PAC Register PAC.0 0 0 0 0 1 1 PAC Register PAC.1 0 0 1 1 0 1 Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option 3/4 CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. If the CLR WDT1 and CLR WDT2 option is chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT, otherwise the WDT may reset the chip due to a time-out. Buzzer Output The Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complimentary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option is used to select from one of three buzzer options. The first option is for both pins PA0 and PA1 to be used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. The buzzer is driven by the internal clock source, fS, which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22 to fS/29. PA data Register PA.1 X X X X X X
PA data Register PA.0 0 1 0 1 0 X
Output Function PA0=0, PA1=0 PA0=BZ, PA1=BZ PA0=0, PA1=Input PA0=BZ, PA1=Input PA0=Input, PA1=0 PA0=Input, PA1=Input
PA0/PA1 Pin Function Control Note: X stands for dont care
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In te r n a l C lo c k S o u r c e
P A 0 D a ta
B Z O u tp u t a t P A 0
P A 1 D a ta
B Z O u tp u t a t P A 1
Buzzer Output Pin Control The clock source that generates fS, which in turn controls the buzzer frequency, can originate from two different sources, the Int.RCOSC (Internal RC oscillator) or the System oscillator/4, the choice of which is determined by the fS clock source configuration option. Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio. There are no internal registers associated with the buzzer frequency. If the configuration options have selected both pins PA0 and PA1 to function as a BZ and BZ complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low, both pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA register has no control over the BZ buzzer pin PA1. If configuration options have selected that only the PA0 pin is to function as a BZ buzzer pin, then the PA1 pin can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output by setting bit PAC0 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer output, if set low pin PA0 will remain low. In this way the PA0 bit can be used as an on/off control for the BZ buzzer pin PA0. If the PAC0 bit of the PAC port control register is set high, then pin PA0 can still be used as an input even though the configuration option has configured it as a BZ buzzer output. Note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the configuration option selection and force the pin to always behave as an input pin. This arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit. Note:The above drawing shows the situation where both pins PA0 and PA1 are selected by configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as outputs. The data setup on pin PA1 has no effect on the buzzer outputs. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the Internal oscilla-
tor (Int.RCOSC) keeps running (if the Internal oscillator is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and starts recounting (if the WDT
clock source is from the Internal RC oscillator).
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * The LCD driver keeps running if the IRC clock is en-
abled; IRCC=0 and LCD on HALT mode set to ON. The system leaves the HALT or IDLE mode by means of an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialisation, and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, and leaves the others in their original state.
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The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin of port A can be independently selected to wake-up the device using configuration options. After awakening from an I/O port stimulus, the program will resume execution at the next instruction. However, if awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the HALT status, the system cannot be awakened using that interrupt. If a wake-up events occur, it takes 1024 tSYS (system clock periods) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider WDT Timer/Event Counter Input/output Ports Stack Pointer 000H Disabled Cleared Cleared. After master reset, WDT starts counting Off Input mode Points to the top of the stack
V
DD
0 .0 1 m F * 100kW RES 10kW 0 .1 m F *
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
The WDT time-out during HALT or IDLE differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to their initial conditions once the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
HALT W DT E x te rn a l C o ld R eset
W a rm
R eset
RES SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
OSC1
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power-up. Awaking from the HALT state or system power-up, the SST delay is added. Rev. 1.10 14
Reset Configuration
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The register states are summarized below: Register MP0 MP1 BP ACC Program Counter TBLP TBLH MODE STATUS INTC0 TMR0 TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC ADCR ADCD WDTC WDTD INTC1 CHPRC Reset (Power On) 1xxx xxxx 1xxx xxxx ---- ---0 xxxx xxxx 0000H xxxx xxxx --xx xxxx --0- 01---00 xxxx -000 0000 xxxx xxxx 0000 1000 xxxx xxxx xxxx xxxx 0000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 x000 ---- -111 ---- ss01 0000 0000 ---0 ---0 0000 0000 WDT Time-out RES Reset (Normal Operation) (Normal Operation) 1uuu uuuu 1uuu uuuu ---- ---0 uuuu uuuu 0000H uuuu uuuu --uu uuuu --0- 01---1u uuuu -000 0000 xxxx xxxx 0000 1000 xxxx xxxx xxxx xxxx 0000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 x000 ---- -111 ---- ss01 0000 0000 ---0 ---0 0000 0000 1uuu uuuu 1uuu uuuu ---- ---0 uuuu uuuu 0000H uuuu uuuu --uu uuuu --0- 01---uu uuuu -000 0000 xxxx xxxx 0000 1000 xxxx xxxx xxxx xxxx 0000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 x000 ---- -111 ---- ss01 0000 0000 ---0 ---0 0000 0000 RES Reset (HALT) 1uuu uuuu 1uuu uuuu ---- ---0 uuuu uuuu 0000H uuuu uuuu --uu uuuu --0- 01---01 uuuu -000 0000 xxxx xxxx 0000 1000 xxxx xxxx xxxx xxxx 0000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 x000 ---- -111 ---- ss01 0000 0000 ---0 ---0 0000 0000 WDT Time-out (HALT)* 1uuu uuuu 1uuu uuuu ---- ---u uuuu uuuu 0000H uuuu uuuu --uu uuuu --u- uu---11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu 0000 x000 ---- -uuu ---- uuuu 0000 0000 ---u ---u uuuu uuuu
Note: * stands for warm reset u stands for unchanged x stands for unknown s for special case, it depends on the option table (please see the WDT chapter for the detail)
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Timer/Event Counter Two timer/event counters are implemented in the microcontroller. Timer/Event Counter 0 contains an 8-bit programmable count-up counter whose clock may come from an external source or an internal clock source. An internal clock source comes from fSYS or the Internal RC. Timer/Event Counter 1 contains a 16-bit programmable count-up counter whose clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4 or Internal RC selected by a special function register option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are two registers related to the Timer/Event Counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Writing to TMR0 puts the starting value in the Timer/Event Counter 0 register and reading TMR0 reads out the contents of Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H) and TMR1C (11H). Writing to TMR1L will only put the written data into an internal lower-order byte buffer (8-bit) while writing to TMR1H will transfer the specified data and the contents of the lower-order byte buffer to both the TMR1H and TMR1L registers, respectively. The Timer/Event Counter 1 preload register is changed every time there is a write operation to TMR1H. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading TMR1L will read the confS In t. R C
YS
tents of the lower-order byte buffer. TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and an active edge. The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C) bits define the operation mode. The event count mode is used to count external events, which means that the clock source must come from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count a high or low level duration of an external signal on TMR0 or TMR1, with the timing based on the internal selected clock source. In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the Timer/Event Counter 0 (1) and ends at FFH (FFFFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of INTC0, T1F; bit6 of INTC0). In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR0 (TMR1) pin returns to the original level and resets the T0ON/T1ON bit. The measured result remains in the timer/event counter even if the activated transient occurs again. Therefore, only a 1-cycle measurement can be made until the T0ON/T1ON bit is again set. The cycle measurement will re-function as long as it receives further transient pulses. In this operation mode, the timer/event counter
M U
fT
0
OSC T0S
X
8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC2~T0PSC0 f IN
T0
D a ta B u s T0M 1 T0M 0 T0E 8 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
TM R0
T0M 1 T0M 0 T0O N
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
8 - b it T im e r /E v e n t C o u n te r (T M R 0 )
O v e r flo w to In te rru p t
Timer/Event Counter 0
fS In t. R C
YS
/4 M
OSC T1S
U X
fT
1
D a ta B u s 8 - s ta g e P r e s c a le r 8 -1 M U X T1PSC 2~T1PSC 0 f IN
T1
L o w B y te B u ffe r T1M 1 T1M 0 T1E 1 6 - B it P r e lo a d R e g is te r R e lo a d
TM R1
T1M 1 T1M 0 T1O N
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
H ig h B y te
L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
O v e r flo w to In te rru p t
Timer/Event Counter 1 Rev. 1.10 16 July 4, 2007
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Bit No. Label Function To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT0=fT0 001: fINT0=fT0/2 010: fINT0=fT0/4 011: fINT0=fT0/8 100: fINT0=fT0/16 101: fINT0=fT0/32 110: fINT0=fT0/64 111: fINT0=fT0/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) Defines the TMR0 internal clock source (0=fSYS; 1=Int.RCOSC (Internal RC OSC)) Defines the operating mode T0M1, T0M0= 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMR0C (0EH) Register Bit No. Label Function To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0= 000: fINT1=fT1 001: fINT1=fT1/2 010: fINT1=fT1/4 011: fINT1=fT1/8 100: fINT1=fT1/16 101: fINT1=fT1/32 110: fINT1=fT1/64 111: fINT1=fT1/128 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) Defines the TMR1 internal clock source (0=fSYS/4; 1=Int.RCOSC (Internal RC OSC)) Defines the operating mode T1M1, T1M0= 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMR1C (11H) Register
0 1 2
T0PSC0 T0PSC1 T0PSC2
3
T0E
4 5
T0ON T0S
6 7
T0M0 T0M1
0 1 2
T1PSC0 T1PSC1 T1PSC2
3
T1E
4 5
T1ON T1S
6 7
T1M0 T1M1
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begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (T0ON; bit 4 of TMR0C or T1ON bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON (T1ON) is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON (T1ON) can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, however as this may result in a counting error, it should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/ event counter scheme, the programmer should pay special attention to the instructions which enables then disables the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable results. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR1C can be used to define the pre-scaling stages of the internal clock sources of Timer/Event Counter 1. Input/Output Ports There are 12 bidirectional input/output lines in the microcontroller, labeled as PA and PB, which are mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H or 14H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC) to control the input/output configuration. With this control register, CMOS outputs or Schmitt trigger inputs with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, and 15H. After a chip reset, these input/output lines remain at high levels or in a floating state, depending upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H or 14H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor connected. Take note that a non-pull-high I/O port setup as an input mode will be in a floating condition. Pins PA0, PA1, PA4, PA5 and PA6 are pin-shared with BZ, BZ, TMR0, TMR1 and INT pins respectively. PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ configuration option is selected, the output signals in the output mode of PA0/PA1 can be the buzzer signal. The input mode always retains its original function. Once the BZ/BZ configuration option is selected, the buzzer output signals are controlled by the PA0 data register. The PA0/PA1 I/O function is shown below. PA0 I/O PA1 I/O PA0 Mode PA1 Mode PA0 Data PA1 Data PA0 Pad Status PA1 Pad Status I I I O OOOOOOOO I I I OOOOO
XXCBBCBBBB XCXXXCCCBB XXD0 1 D0 0 1 0 1
X D X X X D1 D D X X I I I D D0 I I B D0 0 B 0 B B
I D1 D D 0
Note: I input; O output D, D0, D1 Data B buzzer option, BZ or BZ X dont care C CMOS output
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V C o n tr o l B it Q D CK S Q PU
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q M U X
W r ite D a ta R e g is te r
PA PA PA PA PA PA PA PA PB
7 0~PB1
4 /T M R 0 5 /T M R 1 6 /IN T
3
2
0 /B Z 1 /B Z
P A 0 /P A 1 B Z /B Z M U X R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly )
EN
O P0~O P7
T M R 0 fo r P A 4 o n ly T M R 1 fo r P A 5 o n ly IN T fo r P A 6 o n ly
Input/Output Ports It is recommended that unused or not bonded out I/O lines should be set as output pins using software instructions to avoid consuming power when in an input state. Charge Pump and Voltage Regulator There is one charge pump and one voltage regulator implement in this device. The charge pump can be enabled/disabled by the application program. The charge pump uses VDD as its input, and has the function of doubling the VDD voltage. The output voltage of the charge pump will be VDD2. The regulator can generate a stable voltage of 3.3V, for the ADC and also can provide an external bridge sensor excitation voltage or supply a reference voltage for other applications. The user needs to guarantee the charge pump output voltage is greater than 3.6V to ensure that the regulator generates the required 3.3V voltage output. The block diagram of this module is shown below.
Band G ap E nhance R R e g u la to r R EF
I F IL
Additionally, the device also includes a band gap voltage generator for the 1.5V low temperature sensitive reference voltage. This reference voltage is used as the zero adjustment and for a single end type reference voltage.
VOBGP C
BG (S F 0:O 1:O
PQST R b its ) ff (s h o rt) n
F IL
RFIL is about 100kW and the recommend CFIL is 10mF. Note: VOBGP signal is only for chip internal used. Dont connect to external component except the recommend CFIL There is a single register associated with this module named CHPRC. The CHPRC is the Charge Pump/Regulator Control register, which controls the charge pump on/off, regulator on/off functions as well as setting the clock divider value to generate the clock for the charge pump. The CHPCKD4~CHPCKD0 bits are use to set the clock divider to generate the desired clock frequency for proper charge pump operation. The actual frequency is determined by the following formula. Actual Charge Pump Clock= (fSYS/16)/(CHPCKD +1).
CHPC2
CHPC1
VOCHP
VOREG
VDD
C h a rg e P u m p ( V o lta g e D o u b le r )
VDD V D D x2
R e g u la to r (3 .3 V )
3 .3 V
ADC
fS
D iv id e r CHPCKD CHPEN
REGCEN
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Bit No. 0 1 Label REGCEN CHPEN Function Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable) Charge Pump Enable/disable setting. (1=enable; 0=disable) Note: this bit will be ignore if the REGCEN is disable Band gap quickly start-up function 0: R short, quickly start 1: R connected, normal RC filter mode Every time when REGCEN change from 0 to 1 (Regulator turn on) This bit should be set to 0 and then set to 1 to make sure the quickly stable. (the minimum 0 keeping time is about 2ms now )
2
BGPQST
3~7
The Charge pump clock divider. This 5 bits can form the clock divide by 1~32. CHPCKD0~ Following the below equation: CHPCKD4 Charge Pump clock = (fSYS/16) / (CHPCKD+1) CHPRC (1FH) Register Charge Pump OFF OFF ON VOCHP Regulator Pin VDD VDD 2VDD OFF ON ON OPA ADC Disable Active Active
REGCEN CHPEN 0 1 1 X 0 1
VOREG Pin Hi-Impedance 3.3V 3.3V
Description The whole module is disable, OPA/ADC will lose the Power Use for VDD is greater than 3.6V (VDD>3.6V) Use for VDD is less than 3.6V (VDD=2.2V~3.6V)
The suggested charge pump clock frequency is 20kHz. The application needs to set the correct value to get the desired clock frequency. For a 4MHz application, the CHPCKD bits should be set to the value 11, and for a 2MHz application, the bits should be set to 5. The REGCEN bit in the CHPRC register is the Regulator/ Charge-pump module enable/disable control bit. If this bit is disabled, then the regulator will be disabled and the charge pump will be also be disabled to save power. When REGCEN = 0, the module will enter the Power Down Mode ignoring the CHPEN setting. The ADC and OPA will also be disabled to reduce power. If REGCEN is set to 1, the regulator will be enabled. If CHPEN is enabled, the charge pump will be active and will use VDD as its input to generate the double voltage output. This double voltage will be used as the input voltage for the regulator. If CHPEN is set to 0, the charge pump is disabled and the charge pump output will be equal to the charge pump input, VDD.
It is necessary to take care of the VDD voltage. If the voltage is less than 3.6V, then CHPEN should be set to 1 to enable the charge pump, otherwise CHPEN should be set to zero. If the Charge pump is disabled and VDD is less than 3.6V then the output voltage of the regulator will not be guaranteed. ADC - Dual Slope A Dual Slope A/D converter is implemented in this microcontroller. The dual slope module includes an Operational Amplifier and a buffer for the amplification of differential signals, an Integrator and a comparator for the main dual slope AD converter. There are 2 special function registers related to this function known as ADCR and ADCD. The ADCR register is the A/D control register, which controls the ADC block power on/off, the chopper clock on/off, the charge/discharge control and is also used to read out the comparator output status. The ADCD register is the A/D Chopper clock divider register, which defines the chopper clock to the ADC module.
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VDSO R v f1 V M + + A m p lifie r U X + + In te g ra to r R B u ffe r
IN T
PW R C o n tro l ADPW REN
VOREG
R v f2 V
CMP
DOPAP DOPAN
C o m p a ra to r
ADCMPO
O n C h ip O ff C h ip DOPAO DCHOP DSRR DSRC DSCC
A D D IS C H 0 A D D IS C H 1
Note: VINT, VCMP signal can come from different R groups which are selected by software registers.
25kW 100kW 27nF
VOREG DOPAN Chopper A m p lifie r
DOPAO
DCHOP B u ffe r
VB
B r id g e S ensor
VA DOPAP
N o te : A ll " R " a n d " C " v a lu e s h e r e a r e fo r r e fe r e n c e o n ly O ff C h ip O n C h ip
The ADPWREN bit, defined in ADCR register, is used to control the ADC module on/off function. The ADCCKEN bit defined in the ADCR register is used to control the chopper clock on/off function. When ADCCKEN is set to 1 it will enable the Chopper clock, with the clock frequency defined by the ADCD registers. The ADC module includes the OPA, buffer, integrator and comparator, however the Bandgap voltage generator is independent of this module. It will be automatically enabled when the regulator is enabled, and also be disabled when the regulator is disabled. The application program should enable the related power to permit them to function and disable them when idle to conserve power. The charge/discharge control bits, ADDISCH1~ ADDISCH0, are used to control the Dual slope circuit charging and discharging behavior. The ADCMPO bit is read only for the comparator output, while the ADINTM bits can set the ADCMPO trigger mode for interrupt generation.
The following descriptions are based the fact that ADRR0=0
C o m p a ra to r 4 /6 V D S O + In te g r a to r DSRR V
A
1 /6 V D S O
ADCMPO
DSRC
DSCC V
C
R
DS
C
DS
The amplifier and buffer combination, form a differential input pre-amplifier which amplifies the sensor input signal. The combination of the Integrator, the comparator, the resistor Rds, between DSRR and DSRC and the capacitor Cds, between DSRC and DSCC form the main body of the Dual slope ADC.
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The Integrator integrates the output voltage increase or decrease and is controlled by the Switch Circuit - refer to the block diagram. The integration and de-integration curves are illustrated by the following. The comparator will switch the state from high to low when VC, which is the DSCC pin voltage,drops to less than 1/6 VDSO. In general applications, the application program will switch the ADC to the charging mode for a fixed time called Ti, which is the integrating time. It will then switch to the dis-charging mode and wait for Vc to drop to less
V
C
than 1/6VDSO. At this point the comparator will change state and store the time taken, Tc, which is the de-integrating time. The following formula 1 can then be used to calculate the input voltage VA. formula 1: VA= (1/3)VDSO(2-Tc/Ti). (Based on ADRR0=0) In user applications, it is required to choose the correct value of RDS and CDS to determine the Ti value, to allow the V C value to operate between 5/6VDSO and 1/6VDSO. Vfull cannot be greater than 5/6VDSO and Vzero cannot be less than 1/6VDSO
V fu ll
V
V z e ro
1 /6 V D S O Ti T c (z e ro ) Tc T c ( fu ll) In te g r a te tim e D e - In te g r a te tim e
Bit No. 0
Label ADPWREN
Function Dual slope block (including input OP) power on/off switching. 0: disable Power 1: Power source comes from the regulator.
1~2
Defines the ADC discharge/charge. (ADDISCH1:0) 00: reserved ADDISCH0~ 01: charging. (Integrator input connect to buffer output) ADDISCH1 10: discharging. (Integrator input connect to VDSO) 11: reserved Dual Slope ADC - last stage comparator output. Read only bit, write data instructions will be ignored. During the discharging state, when the integrator output is less than the reference voltage, the ADCMPO will change from high to low. ADC integrator interrupt mode definition. These two bit define the ADCMPO data interrupt trigger mode: (ADINTM1:0)= 00: no interrupt 01: rising edge 10: falling edge 11: both edge ADC OP chopper clock source on/off switching. 0: disable 1: enable (clock value is defined by ADCD register) ADC resisters selection 0: (VINT, VCMP)= (4/6 VOREG, 1/6 VOREG) 1: (VINT, VCMP)= (4.4/6 VOREG, 1/6 VOREG) ADCR (18H) Register
3
ADCMPO
4~5
ADINTM0~ ADINTM1
6
ADCCKEN
7
ADRR0
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Bit No. Label Function Define the chopper clock (ADCCKEN should be enable), the suggestion clock is around 10kHz. The chopper clock define : 0: clock= (fSYS/32)/1 1: clock= (fSYS/32)/2 2: clock= (fSYS/32)/4 3: clock= (fSYS/32)/8 4: clock= (fSYS/32)/16 5: clock= (fSYS/32)/32 6: clock= (fSYS/32)/64 7: clock= (fSYS/32)/128 Reserved ADCD (1AH) Register
0 1 2
ADCD0 ADCD1 ADCD2
3~7
3/4
LCD Display Memory The device provides an area of embedded data memory for the LCD display. This area is located at 40H to 50H in Bank 1 of the Data Memory. The bank pointer BP, enables either the General Purpose Data Memory or LCD Memory to be chosen. When BP is set to 1, any data written into location range 40H~50H will affect the LCD display. When the BP is cleared to 0, any data written into 40H~50H will access the general purpose data memory. The LCD display memory can be read and written to only indirectly using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. The LCD clock is driven by the IRC clock, which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of LCD frequencies from Int.RCOSC/3 to Int.RCOSC/4. Note that the LCD frequency is controlled by configuration options, which select the internal division ratio.
COM 0 1 2 3 3 2 1 40H 41H 42H 43H 4EH 4FH 50H B it 0
SEGMENT
0
1
2
3
14
15
16
Display Memory LCD Driver Output The output structure of the device LCD driver can be either 164, 173 or 172 selectable via configuration option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver is R type only. The LCD driver bias voltage can be 1/2 bias or 1/3 bias by option.
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D u r in g a R e s e t P u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l O p e r a tio n M o d e * COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e lig h te d HALT M ode CO M 0,CO M 1,CO M 2 A ll lc d d r iv e r o u tp u ts N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . * * VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS CD S CD S CD S VLC D VLC D
VLC D VLC D VLC D VLC D
CD CD S CD CD S CD V S CD V S CD V S CD V S CD V S CD V S S S
VLC D LC D LC D LC D LC D LC D LC D
CD CD S S
VLC D VLC D
LCD Driver Output (1/3 Duty, 1/2 Duty, R Type)
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VA VB VC VSS VA VB VC COM1 VSS VA VB VC COM2 VSS VA VB COM3 VC VSS VA VB L C D s e g m e n ts O N C O M 2 s id e lig h te d N o te : 1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D VC VSS
COM0
LCD Driver Output (1/4 Duty)
Low Voltage Reset/Detector Functions There is a low voltage detector, LVD, and a low voltage reset circuit,LVR, implemented in the microcontroller. These two functions can be enabled/disabled by configuration options. Once the LVD option is enabled, the user can use the MODE.3 bit to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from bit MODE.5. The MODE register definitions are listed below. Bit No. 0~1, 4, 6~7 2 3 5 Label 3/4 IRCC LVDC LVDO Unused bit, read as unknown In HALT mode, IRC clock enable or disable selection bit. 0: IRC clock enable and Int.RCOSC on. 1: IRC clock disabled. LVD enable/disable (1/0) LVD detection output (1/0) 1: low voltage detected, read only. 0: low voltage not detected. MODE (09H) Register Function
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The LVR has the same effect or function as the external RES signal which performs a device reset. When in the Power Down Mode, both LVR and LVD are disabled. The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as what might happen when changing a battery, the LVR will automatically reset the device internally.
V 5 .5 V
DD
The LVR includes the following specifications:
* The low voltage, which is specified as 0.9V~VLVR, has
to remain within this range for a period of time greater than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it will not perform a reset function.
* The LVR has an OR function with the external RES
signal to perform a chip reset.
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since a low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode.
Operation Mode The device has three operational modes. The system clock comes from external RC or crystal oscillator, and whose operational modes can be either Normal, IDLE or HALT mode. These are all selected by the software. HALT Instruction Not executed IRCC x 0 Executed 1 Disabled Off Disabled and Int. RCOSC OFF Off HALT WDT 3/4 x Enabled Ext. RC Oscillator On Off Off IRC Clock Enabled Enabled and Int. RCOSC ON Disabled and Int. RCOSC ON System Clock External RC or Crystal Oscillator Off Off Mode Normal Idle HALT
Note: The WDTOSC0:1 register should be set to enable, otherwise, the Int.RCOSC will always be disabled. Refer to the WDT section for the WDTOSC setup details.
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Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. There are two types selection: Crystal OSC or RC OSC fS clock source. There are two types of selections: Int.RCOSC or fSYS/4 WDT clock source selection. There are two types of selections: system clock/4 or Int.RCOSC. WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS, CLR WDT times selection. This option selects the instruction method of clearing the WDT. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both the CLR WDT1 and CLR WDT2 instructions have been executed, can the WDT be cleared. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/22~fS/29. fS means the configuration option selected clock source. Wake-up selection. This option defines the wake-up capability. A falling edge on each external pin on PA has the capability to wake-up the device from a Power Down condition. Bit option. Pull-high selection. Selects pull-high resistors when the I/O in in the input mode. PA and PB ports are bit options. I/O pins shared with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty). LCD bias selection. This option is to determine what kind of bias is selected, 1/2 bias or 1/3 bias. LCD driver clock frequency selection. There are two types of frequency signals for the LCD driver circuits: Int.RCOSC/3~Int.RCOSC/4. LCD ON/OFF when in Power Down Mode selection LVR selection. LVR enable or disable option LVD selection. LVD enable or disable option INT trigger edge selection: disable; high to low; low to high; low to high or high to low Partial-lock selection: Page0~3, Page4~6, Page7.
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Application Circuits
V
DD
0 .0 1 m F * 100kW 0 .1 m F
VDD RES
C O M 0 ~ C O M 3 /S E G 1 6 SEG 0~SEG 15 LCD Panel
10kW
0 .1 m F * VSS OSC C ir c u it
VREG
VLCD
P A 0 /B Z
L C D P o w e r S u p p ly
OSC1 OSC2
S e e r ig h t s id e
S ensor DOPAP DOPAN
25kW
P A 1 /B Z
PA2
DOPAO DCHOP
PA3
P A 4 /T M R 0
DSRR
300kW
P A 5 /T M R 1 V
DD
DSRC 47mF DSCC VSS VOREG VOBGP 10mF 10mF VOCHP VOBGP CHPC1 CHPC2 H T 4 6 R 7 3 D -1 PB0~PB3 P A 6 /IN T R PA7
470pF
OSC
OSC1 fS
YS
R C S y s te m 100kW SC
O s c illa to r < 2 .4 M W
/4
VREG 10mF
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
47mF
C1
C2 R1
OSC2 OSC C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.10 28 July 4, 2007
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Instruction Set
Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.10 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 32 July 4, 2007
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
52-pin QFP (1414) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.3 13.9 17.3 13.9 3/4 3/4 2.5 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 17.5 14.1 3/4 3/4 3.1 3.4 3/4 1.03 0.2 7
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HT46R73D-1
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
43
July 4, 2007

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